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-- Company: 
-- Engineer: 
-- 
-- Create Date: 12/04/2022 07:43:04 PM
-- Design Name: 
-- Module Name: alu2bcd - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity alu2pmod is
  Port ( 
        a                    : in  std_logic_vector(2 downto 0);
        b                    : in  std_logic_vector(2 downto 0);
        ctr                  : in  std_logic;
        digit_selection_in   : in  std_logic;
        result               : out std_logic_vector(3 downto 0);
        seven_segment        : out std_logic_vector(6 downto 0);
        digit_selection_out  : out std_logic
        );
end entity alu2pmod;

-- Fill with your own code

architecture Dataflow of alu2pmod is

begin



end architecture Dataflow;