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-- Company: 
-- Engineer: 
-- 
-- Create Date: 06/09/2024 10:11:53 PM
-- Design Name: 
-- Module Name: FSM_Detector - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FSM_Detector is
    port(clk            : in std_logic;
         reset          : in std_logic;
         enable         : in std_logic;
         data_in        : in std_logic;
         detect_seq     : out std_logic
         );
end FSM_Detector;

architecture Behavioral of FSM_Detector is

signal enable_debounced, enable_debounced_edge_detection : std_logic;

component debouncer is
	port (clk       : in std_logic;
	      reset     : in std_logic;
		  enable	: in std_logic;
		  enable_debounced  	: out std_logic
		  );
end component;

component edge_detection is 
	port (clk      : in std_logic;
	      reset    : in std_logic;
		  enable_debounced	   : in std_logic;
		  tick	   : out std_logic); 
end component; 

component sequence_detector is
    port(
		clk			: in std_logic; 
		reset		: in std_logic; 
		enable		: in std_logic; 
        data_in     : in  std_logic;
        detect_seq 	: out std_logic
		);
end component;

begin
	deb: debouncer
	port map (
		clk => clk,
		reset => reset,
		enable => enable,
		enable_debounced => enable_debounced
		);

	edge: edge_detection
	port map (
		clk => clk,
		reset => reset,
		enable_debounced => enable_debounced,
		tick => enable_debounced_edge_detection
		);

	seqdet: sequence_detector
	port map (
		clk => clk,
		reset => reset,
		enable => enable_debounced_edge_detection,
		data_in => data_in,
		detect_seq=> detect_seq			
		);
		
end Behavioral;