library ieee;
use ieee.std_logic_1164.all;

entity edge_detection is 
	port (  clk   : in std_logic;
	        reset : in std_logic;
			enable_debounced : in std_logic;
			tick  : out std_logic); 
end edge_detection; 

architecture gate_level_arch of edge_detection is

signal delay_reg: std_logic;

begin
   -- delay register
   process (clk,reset)
   begin
      if (reset='1') then
         delay_reg <= '0';
      elsif (clk'event and clk='1') then
         delay_reg <= enable_debounced;
      end if;
      
   -- decoding logic 1st
      tick <= (not delay_reg) and enable_debounced;

   end process;
   
   -- decoding logic 2nd
--      tick <= (not delay_reg) and enable_debounced;

end gate_level_arch;